1. Field of the Invention
The present invention relates to a microcomputer with a built-in motor control circuit for controlling, mainly, a three-phase inverter motor.
2. Description of the Related Art
Conventionally, when controlling an AC motor, mainly, a three-phase inverter motor by utilizing a microcomputer, a configuration as shown in FIG. 1 and FIG. 2 was adopted.
FIG. 1 is a block diagram showing a circuit configuration for controlling the three-phase inverter motor.
In FIG. 1, symbol 501 designates a-microcomputer, in which a CPU, a ROM and a RAM which are memories, a timer, a clock oscillator and so on are built in. It is also possible to constitute the microcomputer 501 with a single chip.
Symbol 502 designates an additional circuit, which converts a PWM output waveform composed of a pulse width modulation waveform signal (herein after abbreviated as PWM) generated by the microcomputer 501 into an inverter output waveform. As a result, a three-phase inverter waveform composed of three-phases of U, #U, V, #V, W, #W (# designates an inverted signal) necessary for driving control of a motor is obtained, and this is given to the motor, not shown, as motor drive signals.
As a practical apparatus, as shown in FIG. 2, it is used as a motor control unit consisting of printed wiring board 503 onto which the microcomputer 501 and the additional circuit 502 are mounted.
However, when adopting the configuration as shown in FIG. 1, the additional circuit 502 is required besides the microcomputer 501, and when mounting on the printed wiring board 503 as shown in FIG. 2, it is problematic in that a mounting area becomes larger and susceptible to effects of external noises. Furthermore, since the additional circuit 502 including various components is required besides the microcomputer 501, the fact resulting in a high cost.
In view of such circumstances, the inventors have proposed the invention which has been disclosed in U.S. Pat. No. 5,013,985 (Japanese Patent Application Laid-Open No. 3-70475 (1991)).
In the invention disclosed in the U.S. Pat. No. 5,013,985, as the configuration is shown in a block diagram of FIG. 3, a CPU 501a, a RAM 501b, a ROM 501c, an oscillator 501d, a timer 501e, a motor control circuit 504 and so on are constituted on a chip as the microcomputer 501. The problems of large mounting area and the effects of external noises as seen in the above-mentioned conventional example are attempted to be solved by adopting such configuration.
A microcomputer for controlling an AC motor is disclosed in "FIND" Vol. 9 No. 2 (March 1991) issued by Fujitsu Limited. In the following, this microcomputer will be described as the conventional example.
FIG. 4 is a block diagram showing a configuration of the above-mentioned microcomputer as the conventional example.
In FIG. 4, reference symbol la designates a CPU (central processing unit), symbol 1b designates a RAM, symbol 1c designates a ROM, symbol 1d designates an oscillator, symbol 1e designates a general-purpose port, symbols if and 1g designate interruption-related control circuits, symbol 1h designates a watch dog timer, symbol 1i designates a timer unit, symbol 1j designates an 8-bit reload timer, symbol 1k designates a PWM timer module, symbol 11 designates an A/D converter, symbol 1m designates a UART, and symbol In designates an I/O serial extension interface, which are interconnected by an internal bus 1o and constituted on one chip as a one-chip microcomputer.
FIG. 5 is a block diagram showing a configuration of the above-mentioned timer unit 1i shown in FIG. 4.
In FIG. 5, symbols 2a to 2d designate output compare registers 0 to 3, symbols 2f to 2i designate compare buffer registers 0 to 3, symbol 2j designates a time counter, symbol 2k designates a timer control register, symbol 21 designates a timer interruption control register and symbol 2m designates a compare register.
FIG. 6 is a block diagram showing a configuration of the above-mentioned 8-bit reload timer 1j shown in FIG. 4.
This timer 1j functions as a short circuit check timer (hereinafter abbreviated as a dead time timer) as to be described later. In FIG. 6, symbol 3a designates a timer control register, symbol 3b designates a timer data buffer, symbol 3c designates flip-flops, symbol 3d designates port selectors, and symbol 3e designates an 8-bit reload timer.
FIG. 7 is a block diagram showing the dead time timer shown in FIG. 6 and the timer unit shown in FIG. 5 in combination.
In FIG. 7, symbol 4a on the timer unit side designates a 16-bit timer (corresponding to the timer counter 2j in FIG. 5), symbol 4b designates a U-phase compare buffer (corresponding to the compare buffer register 0 2f in FIG. 5), symbol 4c designates a V-phase compare buffer (corresponding to the compare buffer register 12g in FIG. 5), symbol 4d designates a W-phase compare buffer (corresponding to the compare buffer register 2 2h in FIG. 5), symbol 4e designates a period setting compare register (corresponding to the compare buffer register 3 2i in FIG. 5), symbols 4f to 4i designate output compare registers 0 to 3 (corresponding to the output compare registers 0 2a to 3 2d in FIG. 5), symbol 4j designates a data buffer and symbol 4o designates a compare register (corresponding to the compare register 2m in FIG. 5).
Symbol 4k on the dead time timer side designates a timer data buffer (corresponding to the timer data buffer 3b in FIG. 6), symbol 41 designates a dead time timer (corresponding to the 8-bit reload timer in FIG. 6),symbol 4m designates flip-flops (corresponding to 3c in FIG. 6), and symbol 4n designates port selectors (corresponding to 3d in FIG. 6).
In FIG. 7, symbols RT00 to RT05 designate output ports of respective phases.
FIG. 8 is a block diagram showing a configuration of the above-mentioned A/D converter 11 shown in FIG. 4. In FIG. 8, symbol 13a designates a selector, symbol 13b designates an A/D mode register, symbol 13c designates a comparator, symbol 13d designates a resistance ladder, symbol 13e designates an A/D conversion data buffer and symbol 13f designates a decoder.
Next, the operation of the conventional microcomputer for AC motor control having the aforementioned configuration is described.
First, a PWM period is set in the period setting compare register 4e (compare buffer register 3 2i). The content set in the period setting compare register 4e (compare buffer register 3 2i) is transferred to the output compare register 3 4i (output compare register 3 2d) when the content of the timer 4a (timer counter 2j) becomes "0000H" (H represents a hexadecimal digit). At the same time, when the content of the timer 4a (timer counter 2j) becomes "0000H", interruption is produced by the CPU 1a, and by the interruption processing, data of the period setting compare register 4e (compare buffer register 3 2i) is updated.
Meanwhile, a variation timing of the PWM waveform is set in the U-phase compare buffer 4b (compare buffer register 0 2f). The content set in the U-phase compare buffer 4b (compare buffer register 0 2f) is transferred to and held in the output compare register 3 4i (output compare register 0 2a), when the content of the timer 4a (timer counter 2j) becomes "0000H". Then, when a value of the timer 4a (timer counter 2j) and a value held by the output compare register 3 4i (output compare register 0 2a) are coincided, output levels of the corresponding ports, in this case the output port RT00 for the U-phase and the output port RT03 for the #U-phase, are inverted.
As data used by these compare buffer registers, data obtained by the A/D converter 11 and measuring timers (timer unit 1i etc.) built in the microcomputer are frequently used.
The A/D converter 11 converts analog input values from the outside into digital values for use as compare data of register values of the compare buffer registers 2f, 2g, 2h, 2i and so on or operation data for obtaining the register values.
As the operation of the conventional A/D converter, as shown in FIG. 8, in the case of A/D conversion of five inputs of analog input terminals AN0 to AN4, with respect to analog input information, the analog input terminals AN0 to AN4 were equally sampled repetitively in sequence as shown in a schematic diagram of FIG. 9, regardless of necessary frequencies of the sampling period.
Since the conventional microcomputer with built-in motor control circuit is constituted as aforementioned, in the case of changing the content of start level of the PWM output waveform optionally at every period, or in the case of changing the frequency and the like of the timer data or clock, usually variables must be rewritten by the interruption of the programs executed on the CPU. Thus, when the data are rewritten, a heavy burden is imposed on the CPU. In the case of controlling the high frequency inverter waveform, there is a possibility that the CPU processing speed is not enough and the data can not be updated in real time.
Also, in the A/D converter used in the conventional microcomputer with built-in motor control circuit, it is not operated so as to change the sampling period responsive to necessary frequencies with respect to respective analog input information, and hence, unnecessary samplings are interposed and the sampling time of the A/D conversion is prolonged as a whole.
In the case of using the A/D conversion value thus obtained in PWM output data and the like, since the sampling frequency of the A/D conversion is constant regardless of the necessary frequencies, there is a possibility that the data can not be updated in time.